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SPIRIT IP-XACT controlled ESL Design tool utilized to a network-on-Chip Platform | I10-003 Cheatsheet and real questions

Emmanuel Vaumorin and Maxime Palus, Magillem Design ServicesFabien Clermidy and Jérôme Martin, CEA Leti – Minatec


network-on-Chip is a very lively box of research of the contemporary years. compared to classical bus-primarily based conversation schemes, it implies ingenious mechanisms in addition to new ways of wrapping intellectual residences, giving more communique capabilities. To take care of the gadget design complexity, enhanced electronic gadget level design environments are essential. The goal of this paper is to consider the benefits of an IP-XACT based atmosphere utilized to community-on-Chip design. They display the stage of automation done in the design circulation, talk about its effectivity for the design and verification steps, and propose advancements.


network-on-Chip (NoC) systems are an alternative to the trendy bus architectures [2]. offering a verbal exchange-centric strategy of a design, they aim at overcoming the obstacles of buses due to a higher wire efficiency and a guide for new communication-centric schemes [4]. due to the NoC paradigm, both the design and utility mapping are claimed to be simplified.

youngsters, earlier than this dream turns into authentic, productive strategies for NoC implementation must be set-up. indeed, NoC architectures tackle complicated methods on Chip (SoC), which maybe enclose dozens of IP cores. evaluate the most applicable NoC topology, plug the IP cores on it, simulate and validate the performances of the got design, and possibly change IP cores’ relative positions on the NoC to Strengthen effectivity, are ordinary challenges met by a NoC-based mostly SoC dressmaker. to be able to tackle this complexity and discover the expertise design area at cost effective time and effort, committed equipment should be used.

numerous solutions are proposed in the literature. The Polaris framework [8] presents an entire construction chain including equipment for utility site visitors modeling, excessive-stage design exploration, and backend-stage projections and validations. Its design-space exploration plays on the NoC topology and on its high-quality of provider (QoS). the same device suite has also been exhibited for the ×pipes architecture [7], including NoC synthesis and know-how projection. As regards the Ætheral structure [3], its linked tools offer monitoring facets for debug.

during this paper, they consider the FAUST2 platform, sequel of the FAUST one [5]. It proposes an information streaming verbal exchange model to assure the homogeneity of statistics transfer administration for all IP cores. An adaptable Configuration and conversation controller (CC) ensures the interfacing between IP cores and the NoC. in contrast to the NoC solutions introduced above, the place the representations of IPs are device-selected, the chosen method to deal with the complexity of FAUST2 NoC design, and enrich the time to validation, turned into to use a common and unified representation of the entire equipment to ensure information consistency at every degree of the design circulate. The aspect was to at ease the error-susceptible operation of rewriting the outline of a single IP for distinctive functions, which often leads to mismatch between the different types.

The IP-XACT usual for IP description [9] goals at featuring SoC designers with this sort of unified mannequin. it's an XML based mostly open typical intended to target the needs of business, defined by the SPIRIT consortium. This non-profit firm provides a unified set of necessities for documenting IPs the usage of meta-data. These meta-statistics can then be used for configuring, integrating, and verifying IPs in superior SoC design and interfacing tools the usage of normalized APIs. They may also be used to entry design meta-facts descriptions of complete systems.

To consider the merits that IP-XACT may bring to FAUST2- based mostly SoC design, an IP-XACT compliant toolset known as Magillem has been chosen. Magillem supports superior functionalities described by means of the normal, just like the ability to run code turbines in accordance with IP-XACT APIs, and facilities like a graphical design editor, tooling for IP import and packaging, design assembly and circulate control.

The FAUST2 NoC platform is special in the subsequent area. The main configuration parameters are extracted in order to aspect out the design complexity. area three indicates how IP-XACT may also be used to deploy and manage a complete ESL movement in keeping with a 4-step method: library packaging, design meeting and verification, move manage, and superior movement structure. section 4 then gifts the work realized to adapt and personalize the Magillem framework to the FAUST2 NoC platform. ultimately, got outcomes and barriers, as well as future possible extensions of the move, are discussed.


The FAUST2 community-on-Chip structure pals to every IP core an entire communique and Configuration controller (CC) (determine 1). This area describes its main facets. Flexibility of the proposed structure is highlighted, and the ESL circulation requirements are deduced.

determine 1. IP integration within the FAUST2 NoC.

2.1 CC Overview

determine 2. communication Controller overview.

determine 2 suggests a regular instance of a CC. 4 constituents can also be extraordinary, each made from a number of subcomponents with powerful interactions between them:

  • communique management, together with movement handle, QoS, in addition to communique scheduling aspects, permitting allotted conversation management.

  • CC core configuration management is capable of address not most effective static or off-line configuration, but additionally dynamic: a configuration may well be loaded inner the IP core best when mandatory.

  • check & Debug points, provided through a verify wrapper and via runtime traces and dump mechanisms, that allow precise manage of an utility’s development.

  • 2.2 Core/CC Interface

    To be connected to a CC, an IP core has to suit the interface shown figure 3. This interface consists of a classical tackle/records configuration port, inputs and outputs for statistics flows, execution/fame signals to delivery and control computation inside the IP core, and a few subsidiary indicators, e.g. for verify applications. up to 4 cores may also be associated with a single CC, which absolutely influences the CC: it modifies the number of enter and output flows, and also some inner services. at last, the wiring between CC’s blocks is also impacted.

    furthermore, and reckoning on the IP core (elementary hardwired functions as much as complicated reconfigurable cores), some interface alerts may also be ignored and the width of some others may also be modified. for instance, BIST alerts are vital in case of memory blocks presence, whereas size_released’s width depends on the core administration of its reminiscence and might range a lot from one core to another.

    determine three. CC and core interface.

    2.3 communication & flow manage points

    apart from classical facets of a network interface (e.g. message constructing, circulate manage and QoS), the CC gives an superior integrated communication scheduler. The communications as well as their sequence, are interpreted and played by means of the CC, so that advanced operations can also be performed devoid of the need of intermediate reconfigurations by way of an exterior controller, e.g. a CPU core.

    depending on the IP core, the CC can manage as much as 4 enter and 4 output flows, which modifies the variety of blocks of the CC (e.g. numbers of OCCs, see determine 2). The variety of configurations, as well as the complexity of the scheduling, are strongly dependent on both the IP core and its use inside the complete SoC: the same IP core may be linked to distinct CCs, depending on the capabilities it realizes within the utility movement.

    2.4 Reconfiguration dealing with

    The downsides of a flexible communique controller are (1) an IP core may additionally ought to be reconfigured right through a conversation sequence, in an effort to recognise the global applicative sequence and (2) the number of required configurations, both for communications or for IP cores, could be very small or rather huge. To resolve the primary aspect, a scheduler of IP core configurations, that supports the same sequences as for communications, is built-in within the CC. The 2nd point raises the equal problem of configurations storing for IP core as for the communications, in order to play an entire sequence. reckoning on each the variety of core registers to configure and the number of different configurations necessary, the mandatory memory might possibly be huge, or within the contrary very small. The FAUST2 strategy to resolve this difficulty consists in a configuration cache mechanism, the CC and the IP core are capable of store one or several configurations, and when a cache-miss happens, i.e. a needed configuration is not kept in the neighborhood; the CC is in a position to immediately request it to a really good IP core.

    The cache measurement of the core and the corresponding control are for this reason configurable. Core’s dissimilar configurations are dealt with through a slotid sign (see figure three) which is an non-compulsory characteristic.

    2.5 ESL circulate requirements

    As showed above, the particularity of the CC resides in its excessive degree of flexibility: the variety of cores and enter/output flows, the communication and configuration complexity, and examine capabilities are examples of points which will also be set at designtime to be sure an ideal matching between the IP, the capabilities of its linked CC and software-degree requirements. Such an method avoids over-sizing of communication-committed components, saves vigour and improves performance. The counterpart is the need to have a tremendously able and versatile design ambiance. excessive-stage descriptions, corresponding to SystemC/TLM1 [6] need to even be supported with a view to accelerate the simulation of complex programs.

    From a NoC generation point of view, the requirements of a design go well with are: (1) to contend with not obligatory alerts and blocks, (2) to assist diverse widths for a sign, (3) to be able to adjust the parameters of every CC subcomponent, and in definite cases to generate distinct services for a equal block, (four) to connect the subblocks to attain the correct CC, (5) to handle different representations of a identical component and (6) to enable the closing integration of the regarded accessories in an entire design. In other words, the tool suite needs to be able to present an efficient entry to all the design parameters and functions, and to have a unified representation for all the models describing the blocks. The subsequent area gifts the IP-XACT ordinary, which is theoretically in a position to fulfill the discussed objectives. part four relates the event of an IP-XACT-based design movement for the FAUST2 NoC platform.


    three.1 Overview

    IP-XACT from the SPIRIT consortium is this present day diagnosed by way of the electronics community as an apposite option for managing effectively and effectively the new ESL design flows [1]. however, the migration from a legacy design movement to an extra taking full benefits of IP-XACT requires some heavy and complicated operations. figure four presents the four steps which must be accomplished. they're certain in right here subsections.

    3.2 IP Description

    The goal of this first step is to equipment all the accessories of an IP library into XML data based on the IP-XACT schema, which describes the syntax and semantic rules for the description of three sorts of facets: the bus definitions, the components and the designs (wherein accessories are instantiated). as a result the intention of the IP packaging is to fill in for every part the XML fields that describe its attributes: real ports, interfaces, parameters, generics, register map, physical attributes, etc. a crucial a part of the schema is committed to referencing the information involving the distinctive views of a part: a view may well be as an example a simulable model in a specific language (VHDL, Verilog, SystemC, and so forth) or documentation files (e.g. PDF, HTML, Framemaker). This work facilitates future reuse of present accessories, as a result of all of their elements are quite simply purchasable for its integration and configuration in an even bigger equipment, because it should be defined within the next step.

    figure four. A 4-step methodology to construct ESL flows.

    3.three device Description and Verification

    After the packaging step, is it viable to import, configure and integrate accessories into the equipment, collect the design, unravel connections issues, and automate design initiatives, consequently lightening the verification steps. Some instance of the use of IP-XACT at this level are:

  • Partial or full automation of design assembly and configuration, via TGI2-primarily based turbines that can instantiate, configure and fix accessories in response to chosen design parameters (e.g. abstraction stages of accessories, class of architecture, and many others.).

  • Detection of verbal exchange protocols mismatch, thanks to the bus interface administration, with possible insertion of the necessary adaptors/transactors.

  • technology by way of a TGI generator of the finished netlist defined by using an IP-XACT design, e.g. in SystemC or VHDL.

  • automatic customization of compilation and simulation of designs. indeed a element’s description contains its whole related file route for each and every of its views (TLM, RTL, and so on.), so a generator may construct makefiles, practice competencies componentspecific compilation tags, and launch the compiler or simulator with the acceptable command line.

  • 3.4 stream control

    The third step of the methodology, depicted in the subsequent determine, goals at linking the design actions across the centric IP-XACT database via capability of a committed atmosphere which gives entry to the IP-XACT suggestions. The Magillem tool provides an IP Packager, a Platform meeting device, as well as a Generator Studio to increase and debug further TGI-based turbines. These could be encapsulated inside the IP-XACT illustration of an IP and can for instance without problems launch the execution of a script, getting arguments values from the design description in IP-XACT, or be on the opposite a extra advanced engine, the position of which would be to adjust the design itself (e.g. add connections, insert adapters, or configure components).

    figure 5. principle diagram for an IP-XACT stream.

    Checkers can even be developed and used to verify design suggestions at some element, earlier than going further in the design move. besides, IP-XACT gives mechanisms to explain the sequences of chained mills and checkers.

    three.5 superior movement structure

    This remaining step within the methodology has a excessive capabilities because it exploits all features described previously and makes it possible for the exact implementation of superior ESL actions, akin to structure exploration or software software automated mapping on a hardware platform. These instance display the complexity that needs to be managed via the three first steps: all accessories have to be packaged and their configurability ought to be taken into account; the design meeting automation should still be maximized, whereas any structure option should be handled. eventually, the generator chains, as described up to now, can be configured and managed via supervisor engines: for instance a validation sequence will configure and execute a number of instances the turbines committed to testbench configuration, compilation and simulation.

    four.IP-XACT circulate utilized TO FAUST2

    four.1 Presentation of the ESL Design move

    The evaluation of the design circulation used for the FAUST2 platform (IPs, tools, methodologies, documentation, and many others) has ended in the definition of 5 actions to be installation for the dedicated IP-XACT stream, introduced in figure 6 and specific hereafter.

  • assignment administration: description of the assignment’s folder structure, route place of equipment, project’s parameters administration.

  • IP-XACT packaging of the library: extraction of IP information in folder constitution and advent of metadata data.

  • NoC meeting: era of the instruments’ interfaces, era of the community, configuration of the routers.

  • Compilation: surroundings of parameters, introduction of compilation tasks (makefiles) taking in account the context (TLM/RTL languages), compilers execution.

  • Simulation & efficiency analysis: parameters interface, administration of a simulation mission, launch of simulations, extraction of effects and back annotation in IP-XACT for evaluation.

  • determine 6. ESL design circulate for FAUST2.

    four.2 IP-XACT Packaging of the TLM and RTL add-ons

    The packaging procedure begins with the definition of the conversation protocols between modules. That skill that agencies of physical ports which belong to a identical protocol are described (IP-XACT busDefinition object). The course of each port is distinct for a goal (slave) and for a source (master) use of the considered protocol. some other guidance can even be stored, just like the width of a port, default values, timing constraints, and many others. These busDefinitions have been created manually for the FAUST2 platform using the Magillem built-in IP-XACT editor. concerning the packaging of the interfaces of RTL accessories to create their IP-XACT representation, it has been immediately completed via Magillem with a parsing technique able to extract the counsel from the VHDL mannequin files. For the TLM accessories, this step has been achieved with the IP-XACT editor, which has also been used to replace the representations with complementary suggestions like register illustration, IP-XACT generator inclusion, definition of certain parameters, and many others. After the packaging step, the IP-XACT accessories will also be instantiated and related in a graphical editor to create complete techniques or hierarchical components.

    four.3 CC computerized technology

    The FAUST2 CC, brought in part 2, is fabricated from 13 submodules with a excessive degree of parameterization: number of cores interfaced by the regarded CC, variety of facts inputs and outputs, configuration reminiscence dimension, core status signal width, and so forth. These parameters allow the tuning of the CC to fit the wants of the linked cores. within the relaxation of the paper, the term “selected” qualifies a component that has been configured in response to the parameters chosen through the designer, as adverse to a “normal” factor.

    The total CC generation procedure is handled by Magillem. An IP-XACT description of a common CC, with the minimal interface, has been created, which encloses a generator capable of create a specific CC. standard IP-XACT components have also been created for the entire submodules of the CC. They include the interface, the reminiscence map and a generator to create the corresponding specific CC submodule.

    The era of a specific CC is the result of the execution of a collection of turbines written in Java (counting on an extension of the IP-XACT TGI API) and Perl languages. The extended API adds Magillem certain capabilities like VHDL netlisting of an IP-XACT design and graphical manipulation of design representations (cases and ports area and colors, particular trademarks for accessories), and many others.

    firstly, a well-known CC is instantiated in a design and its embedded generator is referred to as. This generator creates both the IP-XACT and VHDL descriptions of the specific CC, matching the chosen design parameters. As regards the IP-XACT model, assistance concerning the interface, the memory map and the VHDL model file set are captured in an IP-XACT element, whereas structural assistance (subcomponents, connections) are captured in an IP-XACT design.

    each and every submodule of the selected CC is then generated by instantiating the corresponding typical submodule within the CC design and working its embedded generator, which performs right here operations:

  • introduction of the particular IP-XACT submodule.

  • name of a Perl generator which uses a typical template of VHDL code to creates the selected submodule’s RTL model.

  • Substitution of the commonplace IP-XACT part with the generated selected one.

  • Then the connections between submodules and to external ports are introduced to the CC design, and the international CC memory map and file set are created by using gathering the suggestions in all selected submodules, thereby completing the IP-XACT model of the specific CC. determine 7 shows a completely-generated IP-XACT design as it appears on the conclusion of this procedure.

    figure 7. Graphical view of the IP-XACT design of a CC.

    finally the VHDL representation of the finished CC is instantly generated by means of the device, which assembles the in the past created certain VHDL add-ons.

    four.four Design meeting Automation

    The CC generation isn't the simplest automation supplied by means of IP-XACT tools and mills applied to the FAUST2 platform. another TGI generator permits encapsulating and creating IP-XACT views of each SystemC/TLM and VHDL models of the true design of a complete FAUST2-primarily based SoC. It uses a textual content configuration file that carries the desired topology of the NoC interconnect and the identify of IP cores that should still be plugged on it. The SystemC/TLM mannequin of the NoC is created on the equal time by an external generator, along with a collection of configuration files used to software and check the described SoC. anyway, a VHDL netlister makes it possible for to get the corresponding RTL model of the whole SoC in a simple push-button method.

    The identical suitable design technology mechanism is used to create TLM/SystemC simulation testbenches by using adding or replacing some IP cores by debug-selected SystemC contraptions. The user may additionally additionally choose to simulate each regarded IP core at TLM or RTL level, relying on exterior co-simulation equipment.

    figure eight. View of the IP-XACT design of a 3x3 NoC.

    5. comparison AND dialogue

    5.1 advantages for the FAUST2 Design circulate

    The IP-XACT ESL design stream offered in the old part has been demonstrated so as to create a lot of testbenches of FAUST2- based systems. The leading benefits stated throughout these assessments are the convenience of use, the unified mannequin that references all counsel on the design add-ons, and the decreased prolong between the choice of the parameters and the finished meeting of the design.

    Ease of use emphasizes the want of effective IP-XACT equipment such because the Magillem suite, which presents graphical illustration and manipulation of IP-XACT models, hiding the verbosity of XML description data. From a dressmaker point of view, it permits to flick thru the design hierarchy to find and replace any primary counsel. furthermore, mills will also be run in the course of the graphical person interface, and their results automatically seen within the tool. The automation possibilities, through configuration information, scripts and mills, additionally allows to disguise the complexity of operations to the conclusion person: when producing a CC for a core, he most effective has to enter the chosen parameters and get an entire CC after a couple of seconds.

    The intention of getting a unified model that references all suggestions about the add-ons of a platform is to prevent redundancy of assistance between databases: it is fairly regular, for a SoC clothier, to make use of distinct equipment from quite a few CAD companies, each and every one coping with selected tips stored in distinct codecs. In such cases it is difficult to be sure the consistency of the suggestions, because when enhancing some records used by way of one tool you maybe ought to change the facts used through other equipment, this being a customarily error-susceptible operation. IP-XACT presents the possibility to automatically replicate a change on all concerned assistance.

    eventually, the checks confirmed an important discount in the design to validation cycle time. indeed, when a new IP core has been developed in accordance to the FAUST2 core interface structure shown in determine 3, it most effective takes a few minutes to import it and acquire its CC for a given set of parameters. Getting an entire testbench the use of this IP plugged on a NoC is also a rely of minutes. The designer might also for this reason be aware of genuine valueadding tasks, like determining architectural homes (NoC topology, reminiscence size, multithreading help) and simulate the generated design to evaluate the performances. This permits a larger design space exploration than a manual parameterization of the testbench.

    however the use of IP-XACT for the FAUST2 platform has also showed some boundaries or weaker features that are offered within the subsequent subsection.

    5.2 barriers

    essentially the most evident downside of including IP-XACT to an ESL design move is that it requires researching the IP-XACT layout, integrating it into the in the past used design database and packaging all used IPs. notwithstanding this most effective has to be finished as soon as, the latter step can also take a substantial period of time, primarily for complicated systems. indeed now not all advice can be taken into account by way of automatic packagers, and many of the time some statistics, e.g. handle mapping assistance, should be stuffed in manually.

    Of route IP-XACT mills even have required several months to be developed and tuned to the selected wants of the FAUST2 platform, as a way to achieve such a degree of design automation. however, commonly used business CAD equipment do not at the moment help IP-XACT natively. This capacity that, to be certain a correct and automated transmission of design facts to and from these equipment, particular turbines have to be developed and debugged.

    5.three perspectives

    The assessment of IP-XACT potential merits for the FAUST2 design movement could be pursued. both main foreseen advancements contend with the hyperlink of the unified model with backend tools and with the embedded software construction on the FAUST2 platform.

    A hyperlink with backend tools would deliver the chance to replicate in the unified mannequin some traits calculated by way of the tools. for example, for a given core, vigour consumption to recognize common operations, and maximum computing performance, may well be stored within the unified mannequin, and used by means of high degree TLM/SystemC models of a complete device to have simple power and efficiency estimation for an entire utility running on a SoC.

    From the embedded application design factor of view, the unified mannequin already carries a lot of significant suggestions, especially related to tackle mapping. A generator could conveniently solve the error-inclined manner of rewriting the handle map in accordance with the syntax of chosen programming language, in addition to reflect immediately in utility any trade within the hardware tackle map.


    during this paper, they confirmed how an IP-XACT-controlled ESL design flow might also deal with the design complexity of NoC-primarily based SoCs. This typical offers a unified representation of all significant design counsel. within the common FAUST2 case, it makes it possible for a brief integration of an IP core in the design, as well as an automated generation of complete methods.

    however, the can charge of switching from legacy to IP-XACT flows isn't negligible, as it frequently requires manual operations to get a complete description of IPs. in addition, native IP-XACT aid via existing design equipment is enormously pleasing, as for now turbines have to be written to transfer relevant information to the CAD equipment. once these two points are solved, IP-XACT flexibility gives the designers with very beneficial design flow customization and automation amenities.


    [1] Bailey, B., Martin, G. and Piziali, A. 2007. ESL Design Verification. Morgan Kaufmann Publishers, 2007

    [2] Benini, L. and De Micheli, G. 2002. Networks on Chips: a new SoC Paradigm. IEEE Transactions on computers 35, 1, (Jan. 2002), 70-seventy eight.

    [3] Ciordas, C., Hansson, A., Goossens, ok., and Basten, T. 2006. A Monitoring-aware community-on-Chip Design movement. In lawsuits of the ninth EUROMICRO conference on Digital gadget Design. DSD '2006.

    [4] Henkel, J., Wolf, W., and Chakradhar, S. 2004. On-chip networks: a scalable, conversation-centric embedded equipment design paradigm. In court cases of the 17th overseas conference on VLSI Design (June 21 - 24, 2004), 845 - 851.VLSID '04.

    [5] Lattard, D., et al. 2007. A Telecom Baseband Circuit in response to an Asynchronous NoC. In IEEE overseas solid-State Circuits conference Dig. Tech. Papers (Feb. eleven - 15, 2007), 258 - 601. ISSCC '07.

    [6] Open SystemC Initiative (OSCI) homepage.

    [7] Pullini, A. et al. 2007. NoC Design and Implementation in 65nm technology. In proceedings of the first international Symposium on network-on-Chip. NOCS '2007.

    [8] Soteriou, V., Eisley, N., Wang, H., Li, B., and Peh, L. S. 2007. Polaris: A equipment-degree Roadmapping Toolchain for On-Chip Interconnection Networks. IEEE Transactions On Very enormous Scale Integration (VLSI) systems 15, 8 (Aug. 2007), 855 - 868.

    [9] SPIRIT Consortium homepage.

    1 TLM: Transaction level Modelling.

    2 TGI: Tight Generator Interface is the identify of the API defined by SPIRIT for getting access to data kept in an IP-XACT database.

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