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LSI Solutions Free PDF

meeting the challenges of 90nm SoC design | L50-502 PDF Dumps and Questions and Answers

with the aid of Tim Daniels, LSI LogicBracknell, UK

summary:the first quarter of 2003 will herald the first 90nm prototype ability. although, plenty of the industry views the latest node with some trepidation given the physical know-how challenges that emerged within the flow to 0.13ìm.

This paper outlines the a variety of considerations found at the latest 0.13ìm node and the way these are being solved by means of the industry and adopted for 90nm design so that time to market in comparison to outdated generations doesn't turn into a crippling difficulty. it is a ordinary paper supposed to replace these concerned in SoC and IP design on existing implementation challenges.

subject matters mentioned consist of: Voltage, power and reliability issues at the micro level and RTL analysis, Hierarchical design and database wants on the macro level. example methodologies used to conquer these issues are given to be able to demonstrate solutions for 90nm design.

1.0 IntroductionTo design a device-On-Chip (SoC) in 90nm know-how designers simultaneously juggle the twin challenges of controlling both the macro stage with massive complexity issues and the micro stage with small actual concerns at the same time as holding to the standard constraint of Time-to-Market (TTM) so as to get a return on funding.

The complexity at 90nm is daunting. A 10x10mm die might be capable of include massive SoC functionality. An example of a standard 100mm2 design may be:

good judgment 10M Gates (20 x 0.5Mbit blocks, inc CoreWare) reminiscence 39Mbits  (200 circumstances: 1,2,four Port Sync) equipment Flip-Chip 960 (with matched pairs) Clocks 25 (%/MHz: 50/one hundred, 25/200, 25/four hundred) CoreWare 4 off MIPS5Kf + peripherals,ARM7 + peripherals,2x40Gbit SFI5/SONET I/F,10Gbit Ethernet/XAUI I/F, table 1:  instance possible 90nm SoC complexity

2 Micro degree IssuePhysical concerns that designers face raise dramatically under 0.18um. At 90nm the SoC fashion designer is confronted with an array of issues. Key amongst these are: vigour drop, instantaneous voltage drop (IVD), clock, Crosstalk, and reliability concerns (electromigration, yield enhancement). All such design integrity concerns have to be solved for timing, area and energy concurrently to get a working overall solution.

2.1 changing Nature of DelayOver fresh technologies the character of prolong has changed from being in the cells to being within the interconnect technology.

Fig 1:  Relative mobile to interconnect lengthen

Switching from Aluminium/SiO2 to Copper/Lowk has helped cut back this effect but in 90nm interconnect extend will dominate with about 75% of the common delay [Ref 1]. Thinner tightly packed interconnect are the root cause for many of the micro stage concerns discussed below.

2.2 energy Drop

 Fig 2: A Flip-Chip vigour mesh

ensuring an adequate vigor mesh is without doubt one of the largest concerns. At 90nm simplest 1v is purchasable in the core so for under a 5% voltage drop handiest 50mv drop is allowed throughout the mesh. The mesh development is extremely elegant upon the variety of metallic layers, sub-module and memory placement and package category. LSI logic uses in-condo tools to immediately generate a correct with the aid of development energy mesh.

illustration primarily based vigour estimation ideas are used to analyse IR drop to ensure requirements are met. With such little headroom for voltage edition implementation of energy mesh can be key.

2.three Instantaneous Voltage DropPeak dynamic vigour usage, already vital at 130nm, may be primary at 90nm. Instantaneous voltage drop (IVD) concerns will require shut evaluation and the insertion of native on-chip capacitors to evade issues resulting from excessive noise on the vigor mesh. Areas of excessive vigour usage inside the die, certainly memory, PLLs and clock drivers, will need to be handled very carefully during this respect. LSI common sense uses in-house equipment to pre-vicinity on-chip capacitors near these blocks to prevent IVD failures. in addition on-chip capacitor are additionally added put up-placement with a view to in the reduction of effects of IVD on the die. The amount of capacitance added is dependent upon the switching exercise (frequency) of the die and the types of cells used.

 Fig 3: idea of the IVD avoidance

another formulation of decreasing IVD now used is with the aid of replacing standard flip-flops with slower switching models throughout the physical optimisation step of timing closure the place the paths have enough slack time to face this. special Flip-flops are designed for the library principally for this aim.

2.4 ClockAt 90nm clock lengthen and skew can be very complicated to control. The top-quality flows can be based around computerized helpful skew suggestions and should control prolong through branches of the clock via adjusting prolong by way of publish-clock insertion lengthen mobilephone swapping. LSI good judgment makes use of "lsimrs", its physical optimisation tool, to insert clock trees with advantageous clock skew. Clock crosstalk avoidance (by means of sign wire isolation) is developed into such tools in order that the clocks aren't aggressors or victims to regional signal nets.

A aspect improvement of positive clock skew should be to just a little cut back IVD concerns on the die by using spreading the clock edges along diverse clock branches.

Fig four: Graphical description of Crosstalk

2.5 CrosstalkCrosstalk already a standard sign integrity concern at a hundred and eighty/130nm, yet commonly left out in lots of SOC flows today, will turn into critical at 90nm. Crosstalk is led to when an aggressor web working parallel to a further sufferer internet motives false switching (noise) or altered timing (delay) on the sufferer net. cautious analysis, peculiarly of the delta timing caused via the prolong outcomes, takes roughly two weeks for a 3M gate design. This without delay affects design flip-around-time.

An alternative movement that LSI common sense uses is to add crosstalk avoidance placement/optimisation tools to add margin to the wire delays calculated within the layout tools and SDF timing file (lsidelay tool) so as steer clear of having to run these crosstalk avoidance evaluation tools in any respect. This does not work for all designs seeing that those pushing timing cannot stand the further margin. in this case these extra margins must be overridden and the further crosstalk evaluation equipment are run as a substitute.

 Fig 5: Crosstalk Avoidance move

automated avoidance all through routing will eliminate such issues when these equipment definitely come on-line however such tools don't seem to be purchasable today.

2.6 Reliability IssuesMany of the reliability issues considered at 130nm are already addressed via tool automation and methodology adjustments. These consist of:•    metal antennae effects - the place an electron can charge can construct up on long nets all the way through manufacturing and blows up the transistor connected to it. averted by means of inserting diodes or adding steel jogs to the routing to force a layer change. The latter may cause many added vias within the layout which has it be own reliability considerations if now not carefully managed.•    metal Slotting consequences – here is the place broad wires trigger "steel dishing" results due to processing obstacles. avoided by using splitting large wires.•    concurrently Switching Outputs (SSO) – the place noise is injected into the power rails from many output adjustments on the identical time and causes false signal values. prevented with the aid of including vigor/ground pads and by way of I/O isolation.•    tender mistakes – Alpha particles, each naturally taking place and from lead in packaging, may cause state inversion of a flip-flop or memory aspect. With shrinking technology the can charge brought on turns into greater enormous. averted through hardened flip-flops, error correction built into the recollections and by means of fault tolerant equipment architectures.•    memory yield – With reminiscence taking an ever-greater share of the die, roughly 60% in the example above, standard decent die per wafer might be reduce than with pure common sense. prevented by way of adding redundant rows/columns and the use of constructed-In Self restoration (BISR) with the higher embedded reminiscences.

2.6.1 ElectromigrationElectromigration (EM) is a key reliability impact so one can irritate in 90nm. EM is caused by means of decreasing metallic widths and increasing existing density. When overstressed metallic ions are inclined to migrate over time at last inflicting the connection to break. LSI common sense runs "lsisignalem" after placement to set routing rules to be sure that metal and by the use of structures are amazing ample to prevent the EM concerns that can occur on signal nets. post route checking is additionally carried out to be sure that the avoidance turned into successful.

 Fig 6: Electromigration avoidance

2.7 Timing FilesOne of the "small" concerns that are not below handle in all flows these days is that of accurate extend calculation. metal model at 90nm will trigger an unlimited difference in both resistance along the wire and capacitance between the wires. The usual max/min delay numbers are a posh equation of upward push time alongside the nodes varying with R and C, where the worst case R and C doesn't necessarily supply the worst case prolong numbers. LSI common sense makes use of "lsidelay" to generate accurate golden timing suggestions from the RC information, which may well be run on multi-processor machines for pace. producing real superior and worst case numbers from extracted R/C statistics is a non-trivial project where over-simplified algorithms will beginning to fall apart in 90nm. The device can additionally handle various PVT (process/ Voltage/ Temperature) and different factors that have an effect on the common timing.

2.eight steel StackAnother extra physical situation, no longer below manage in all strategies today, is that of the manufacturability and reliability of the copper/Low-okay metal stack [Ref 2]. At 0.18um LSI logic certified Low-okay with an aluminium steel stack. The low-k dielectrics gave large benefits when it comes to cutting back the results of coupling capacitance of the interconnect. At 0.13um LSI good judgment used each Low-k and a copper metal stack. Switching from aluminium to copper has been a steep getting to know curve for the industry but having obtained this beneath manage moving to the 90nm technology node should be rather easy due to the fact the identical basic materials may be used within the metallic stack.

three Macro stage IssuesWhen coping with the "massive" complexity issues, SoC design teams are being compelled to face new challenges of defining and fixing device architectures based mostly round in reality market-available IP after which integrating in-residence designed blocks as crucial to complete the functionality. Controlling the "big" boils all the way down to: determining the appropriate IP to go well with the structure (and vice versa), setting up a great utility and early hardware verification strategy, performing early RTL analysis on developed code, early physical planning, a complete test strategy all coupled carefully with hard mission management and company talents.

3.1 actual RTL optimisationPhysical RTL optimisation analysis is now being identified by way of the business as a crucial device for SoC designers, with a lot of EDA tools fitting accessible. Such equipment realise the actual implementation of the RTL and provides early comments as to negative RTL constructs for you to trigger complications in design.

 Fig 7: Early RTL evaluation offers challenge handle

first rate RTL architecture and coding can shop many man months in project timescales. The RTL evaluation equipment within LSI common sense's FlexStreamTM design movement function fast synthesis, partitioning, placement, and timing evaluation of an RTL block and supply specific counsel about that block.

the sort of device highlights considerations within the RTL that are likely to trigger problems for the design tools later within the flow. LSI logic rules constructed into the tool exceptionally highlight RTL constructs that have brought about complications during the past.  Designers armed with this competencies can then adjust the structure and coding of the RTL to prevent such concerns.

One example of normal considerations is RTL that infers an incredible mux'ing function, regular in conversation swap SOC's, which will be problematic to layout. One option would be to split the mux'ing feature in a distinct way. A 2nd illustration is that of a controller block it truly is shared between two sub-modules and is within the essential timing path for each modules. One solution to here is to replica the controller function locally to each.

The top-quality RTL analysis tools therefore supply a concept of the actual concerns which have been inferred in RTL code even earlier than floorplanning is all started. They supply very quickly feedback on the way to optimise the architecture and coding which is linked directly lower back to the supply RTL code, in a method that early floorplanning/placement equipment effectively can not.

3.2 FloorplanningEarly physical planning of big SoC designs is a pre-requisite. An early floorplan displaying place of the excessive pace I/O, block and memory area quickly offers an idea of the feasibility of the actual design and goes one stage additional than the RTL analysis equipment. for instance, the SFI5 physical layer interface within the design illustration is advanced - 16 differential pairs making 40Gbit/s (16X2.5Gbit/s) - and requires careful placement on the die, the equipment and the board. Such equipment level skill units are non-trivial and totally favorite with a purpose to power items without delay to market with low risk. Floorplanning a 10Mgate design requires targeted routing of world signal and clock nets at this early stage with a view to manage time of flight and define timing and area budgets for the block. up to date device flows, such because the FlexStream Design device, allow hierarchical design methods for each and every of these sub-blocks but it is controlling timing closure early at this correct level it really is the important thing to a fast turn-around-time and finally a a hit product.

 Fig eight: normal Floorplan at 0.13um

4 move-Border IssuesThere is an additional class of considerations that crosses macro and micro degrees, together with look at various, common chip power/temperature and database measurement, that will challenge engineers in 90nm. among the many verify considerations: natural "full scan" caught-at fault insurance test suggestions are beginning to take too long in construction checking out and are more and more proven to have too many look at various escapes, IDDq trying out is becoming much less manageable due to increasing transistor leakage. Silicon carriers, EDA businesses and research institutes are actively working on such concerns and we're prone to see quick evolving examine techniques within the near future including Scan compression, logic BIST, and transition fault coverage.

standard chip vigor will turn into an expanding focus for SoC in 90nm as a result of die temperature has a right away effect on failure expense and hence the reliability of the SoC. strategies used in battery-operated devices for years, akin to sluggish clocking and sleep modes as well because the extra standard gated clocking, grey code addressing and reminiscence splitting will be widespread. EDA tools will need to in reality consider the third axis of vigour (as well as time and area) within the design circulate.

4.1 Database SizesThe final go-border problem to be highlighted is that of file and database dimension. An example of controlling database measurement, and for this reason flip-round-time, is that of the standard timing signoff move nowadays: SPEF files (RC facts) are extracted at chip stage, then SDF information are generated the usage of the silicon seller's golden timing engine and an STA tool will analyze this database. last flat timing runs like this already take a number of days, every intermediate file taking several Gbytes of records, and working handiest on a machine with a 64bit operating equipment. short time period, key equipment reminiscent of LSI good judgment's prolong calculator "lsidelay" that generates the SDF were adapted to run on multi-threaded and multi-processor compute farms. long term the trade will adopt methodologies such as OLA library models (a library with a inbuilt golden timing calculator presented by way of the silicon vendor) and OpenAccess general databases such that extraction, delay calculation and STA analysis will also be achieved in a much greater effective method. using a single database into which all tools can plug will completely evade the numerous intermediate data of varying formats with differing limitations being required. [Ref 1].

 Fig 9: File and database concerns

In generic, the administration project of generating and controlling a machine, utility and human useful resource infrastructure to enable SoC design inside time-to-market constraints might end up being the biggest problem of all. here's especially true because it includes the pass-trade collaboration of silicon providers, EDA providers and gadget residences.

5 SummaryWhen taking a look at quantity creation necessities the need for lowest can charge, smallest die, lowest energy and quickest velocity will at all times push SoC design teams to the innovative of know-how. Foundries are already running early 90nm silicon at an R&D degree and early SPICE suggestions are already obtainable. First sign-off cell libraries are now available whereas the primary IP blocks will be available all over the primary half of 2003 along with prototype capability.

while some may additionally believe the trade is at its lowest ebb for years with stability sheets displaying pink in lots of business sectors, there is already a 90nm SoC infrastructure being put in vicinity with a view to yield leading edge items in the next year. For SoC designers, the should grapple with the technology challenges of 90nm can be here sooner than many had dared hope.

References:1 down to the Wire, Lavi Lev et al, Cadence

2: disasters plague 130-nanometer IC tactics, Ron Wilson, EETimes

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